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Dual Line Interface for Automotive and Avionics Display Products
key word:Aviation, automobile, two-wire interface, display productsWith the expansion of LCD application to other non-traditional computer or consumer electronic products, the capability of existing LCD embedded digital interface can not meet the requirements of the new generation of technical challenges. The most commonly used embedded digital interface LVDS (low voltage differential signal transmission) is about to be eliminated in the transportation (automotive and Aerospace Electronics) and industrial markets it supports. In order to meet and face the above technical challenges, there is a new interface chipset 1 on the market. This product has similar characteristics to LVDS. By using the innovative embedded clock control scheme and wider data serial ratio, the number of interconnections is greatly reduced. As a result, only one differential pair (two-wire) is required to realize interconnection. In addition, this new interface product can also support long cable drive and AC coupling. In order to fully understand the importance of this product, the following author will make a detailed assessment of the needs and challenges to be faced.   Challenge   Whether the interface is digital or analog in nature, the standard requirements for all display interfaces in the transportation and industrial markets are listed below:   *Reduce the number of interconnects   *Supports a wide range of operating temperatures: - 40 ° C to 105 ° C   *Electrochemical or electrical isolation (AC coupling)   *Long distance cable driving capacity: up to 10 meters   In commercial electronic or computer applications, most choose digital interfaces (LVDS and HDMI). Using digital interfaces can not only reduce the cost of the whole system, but also greatly improve the image quality of the whole front panel.   Reducing the number of interconnects can not only greatly reduce the cost of the whole system, but also provide greater flexibility for system wiring and assembly in space constrained applications. More importantly, the reduction in the number of interconnects will simplify the wiring of interfaces and / or other wire harnesses through the base.   In transportation and industrial applications, the interface will be exposed to harsh outdoor environment, so these applications require that all interfaces must be able to work reliably in a wide temperature range (- 40 ° C to 105 ° C, which may not be the most extreme range) within their rated bandwidth.   The electrochemical / electrical isolation of the interface through AC coupling can bring many benefits. From the perspective of interface hardware, AC coupling provides electrical isolation between subsystems. In transportation related environments (such as automobile, aviation and train), this isolation enables the interface to interact with some subsystems in networks with different potentials. Another advantage of electrical isolation is that it provides short-circuit protection from the interface to the power supply for the display subsystem. This is because in any battery powered subsystem, the function of short circuit protection is a necessary condition. Another advantage of AC coupling is that the interface operation can not be affected by the voltage / geometry of any silicon process. For example, in some cases, the data source interface may need to operate at a process voltage of 1.8V, while the receiver interface needs to operate at a silicon process voltage of 3.3V. Long distance cable drive is another necessary condition. In the data source (image processor, DSP and processor) and processor (processor or LCD) In applications where the distance between them may be greater than 10 meters, the interface must be able to support cables up to 10 meters or more without relying on any additional signal recovery and / or electric buffer elements. For example, in the rear seat entertainment system in the car, the on-board entertainment system, and the infotainment system in the bus or subway transportation system, the display will be placed far away The location of the information source.   achievements   In order to meet these stringent requirements, national semiconductor has developed an LVDS SerDes (serial deserializer) chipset ds90c2411 and ds90c1241 that can effectively solve these technical challenges.   Characteristics of SerDes   This chipset will receive up to 24 bit parallel CMOS / TTL potential data and clock sources related to data from graphics or video data sources. Data and clock will be transmitted serially on a single differential pair. 24 bit data can be used to represent display color data (18 bits or 6 bits / color) and control signals (Hsync, Vsync and data enable) . for the maximum synthetic bandwidth of 840mbps, it can support frequencies from 5MHz to 35MHz (which can be extended to 65Mhz in the future).   Capacitors are added to each pin / power supply through the data source on the interface and the differential pair on both sides of the receiver (see Figure 1) , it can effectively realize the AC coupling of the interface connection. The capacitor will effectively block the bias of any DC potential on the connection, so as to successfully isolate the receiver from the data source and their own power supply. The isolation of any DC potential realized by these same capacitors actually only allows higher frequencies (greater than 1MHz) In this case, the serialized signal itself is actually exchanged at a differential potential similar to the LVDS electrical potential ( / - 350 MV). Compared with other types of interfaces, this lower differential swing potential will lead to lower power consumption and EMI efficiency.     Figure 1: two wire serial interface.   Reduced number of interconnects   In this new product, two methods are adopted to greatly reduce the number of Interconnects:   *Embedded clock   *Wide / large serial ratio   Up to 24 bit parallel data and clock input serializer (ds90c241). The serializer converts parallel data into serialized data (24:1), enabling it to be transmitted through differential pairs (two-wire) composed of low-cost copper interconnects. In addition to parallel data, clock (CLK1 and CLK0) and others maintain DC balance and connection integrity (DCB and DCA) The necessary additional bits are also serialized together with the actual data bits (see Figure 2). Embedding the clock into the data can eliminate the clock to data edge skew that may cause data errors when the data and clock are recovered on the deserializer side, and obtain key benefits.Random data locking and hot plug   Another unique feature of this product is that unlike other interface solutions, a reference clock must be used on the deserializer side to identify and / or decode the embedded clock signal. Its deserialization architecture has a unique advantage that all random data patterns can be locked without using any reference clock in the deserializer (RDL, random data locking). RDL features create conditions for another end-user advantage, "hot plug" The characteristics of the deserializer can enable the deserializer to re lock to the serialized data flow that may be effective after disconnection, invalid after disconnection and disconnection when the cable is connected and disconnected. In this case, the interface can be easily re locked without any special clock training mode or special initialization sequence of interface connection.   AC coupling and DC balance   Since the entire interface connection is AC coupled, the interface connection must be vulnerable to DC charges that cause unbalanced density of 1 or 0. Continuous 1 or 0 will establish potential DC potential charges on the connection, which will hinder a state (1 or 0) The correct transition to another state leads to data error. This effect is also called ISI, intersymbol interference 2. Therefore, in order to reduce ISI effect, an integrated DC balance algorithm is adopted in the new interface products of national semiconductor.   Long distance cable drive   In order to obtain a bandwidth of up to 1Gbps (or 840mbps) under a 10 meter cable drive length, clean and large "eye" openings must be obtained at the end of the cable to ensure that the receiving deserializer can reliably recover data. Excessive jitter and signal loss caused by the cable will prevent the "eye" The PLL (phase-locked loop) in the serializer can be precisely designed to reduce or eliminate excessive jitter. In order to overcome the signal loss caused by cable load, a technology called pre amplification 2 is adopted, which essentially overdrive / boost the signal at the switch conversion of the serialized data flow.   Figure 2: serialization configuration and protocol.   conclusion   Through the introduction of National Semiconductor's new SerDes product ds90c241 / ds90c124 SerDes, figure 3 shows a new digital display interface, which is suitable for remote applications with particularly strict and / or harsh requirements, and in SVGA (800X 600) /The working distance at 42 MHz resolution is up to 10 meters. The interface architecture can be easily upgraded to a higher bandwidth to support future display resolutions such as XGA or higher.   Figure 3: typical application - rear seat infotainment and navigation display.
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